Q: What is a synchronous digital design? A: It is the design with the structure compoused generally from D flip-flops and combinatorial logic connected as follows: - connections betwen D/Q pins of DFF is composed of combinatorial logic - CK (clock input of DFF) are connected at the same wire creating common clock tee. Ideally (as model) all DFFs in the design change its output (Q) at the same time the clock edge comes. Q: What is a combinatorial logic? A: It is a part of a digital design providing logic function and composed from combinatorial logic cells. For example: AND, NAND, OR, NOR, XOR, ADD etc. Q: What is a logic synthesis? A: It is a step in a digital flow when a digital design decribed in some language VHDL/Verilog is transformed to a schematic. The schematic is gate-level representation of the design composed of standard cells. Q: What is a ? A: It is Q: What is a ? A: It is Q: What is a ? A: It is |
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