The aim of this part is to summarize staff related to ASIC synthesis and corresponding static timing analysis process. It's focussed on Synopsys Design Compiler and PrimeTime tools.
See below usefull commands---- set-up maximum transition time on all outputs set_max_transition 3 [all_outputs]---- set-up maximum number of fanouts for each of nets in the design set_max_fanout 50.0 [current_design]---- report status about constraints coverage and met/violated report_analysis_coverage---- report all violating report_constraint -all_violators---- report "setup problems" report_timing -delay max -to reg0/d---- report "hold problems" report_timing -delay min -to reg0/d---- adding of constraint and following constraint reset (the constraint is not written to the SDC output) set_max_delay 5 -from reg0/q -to reg1/dcompilereset_path -from reg0/q -to reg1/d
Before usage commands mentioned above use appropriate manual pages.
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