Features
- RISC processor based on Harvard architecture
- 16 instructions
- I/O management as registers
- two's complement arithmetics
- Z, C, O flags
| |
BabyRISC4 |
BabyRISC8 |
BabyRISC16
|
instruction width
|
12 |
20 |
36
|
register width
|
4
|
8
|
16
|
general registers
|
4
|
8
|
16
|
inputs
|
4 x 4
|
4 x 8
|
4 x 16
|
outputs
|
4 x 4
|
4 x 8
|
4 x 16
|
Instruction setJump instructions - JZ, JC, JOMove operations - MOVC, MOVLogic operations - AND, OR, XORShift logic operations - SLL, SLRShift arithmetic operations - SAL, SARCompare operation - CMPArithmetic operations - INC, DEC, ADD | |
|
