A simple ALU (AND/OR/XOR/SHL)

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// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
// ~ --
// ~ Published by: www.asic-digital-design.com
// ~ --
// ~ Description: This is a simple ALU.

// ~   Supported are logical operations

// ~ (AND, OR, XOR, SHL)

// ~ --
// ~   inputs:
// ~     a_in - operand 1
// ~     b_in - operand 2
// ~     op - operation
// ~              00 - AND
// ~              01 - OR
// ~              10 - XOR
// ~              11 - SHL
// ~ --
// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~

module alu_simple ( dout, op, a_in, b_in );
parameter [31:0] n = 8;
output [(n - 1):0] dout;
input [1:0]       op;
input [(n - 1):0] a_in, b_in;

// declaration of signals inside this block
reg [(n - 1):0] dout;

always @ (op or a_in or b_in) // ALU logic
begin
    case (op)
      2'b01: dout <= a_in | b_in;
      2'b10: dout <= a_in ^ b_in;
      2'b11: dout <= a_in << b_in;
      default: dout <= a_in & b_in;
    endcase
end

endmodule

The example in the left column is a Verilog description of very simple ALU.
The ALU is providing only logical operations - AND, OR, XOR and SHL.
It is a pure combinatorial logic without any registers. A case statement selects data to be propagated to the output 'dout'. It is demonstrated at the following figure:

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A simple ALU (AND/OR/XOR/SHL)

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