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Verilog design - simple ALU
Verilog examples - added new items
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01 - BabyRISC processor family
02 - ChildRISC processor family
03 - TeenRISC processor family
04 - AdultRISC processor family
Verilog design (complex blocks)
A multiplier composed of an adder
A simple ALU (AND/OR/XOR/SHL)
simple RISC processor core
SPI interface - to be updated
SPI master - to be updated
SPI slave - to be updated
Verilog examples
Basic components
combinatorial cells - tbu
full adder - tbu
Multiplexers
multiplexer 2 to 1 <mux2to1>
multiplexer 4 to 1 <mux4to1>
multiplexer 8 to 1 <mux8to1>
sequential cells - tbu
D flip-flop
Data latch
JK flip-flop - tbu
T flip-flop - tbu
Design components (building blocks)
1 of N generator
BCD up/down counter
binary up/down counter
Johnson counter
LFSR generator - tbu
Testbench components (models)
Verilog: clock generator
Verilog: reset generator
Testbenches for building blocks
Verilog: testbench for counters
Verilog-operators
Verilog-system tasks
VHDL examples
Design components (building blocks)
VHDL: 1 of N generator
VHDL: BCD up/down counter
VHDL: binary up/down counter
VHDL: Johnson counter
VHDL: n-bit ripple counter
VHDL: shift register
VHDL: state machine (semaphore)
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Verilog design (complex blocks)
>
simple RISC processor core
To be published very soon.
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