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multiplexer 2 to 1 <mux2to1>


// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
// ~ --
// ~ Published by:   www.asic-digital-design.com
// ~ --
// ~ Description:
// ~ -- This is Verilog description of
// ~ --  a multiplexer 2 to 1.
// ~ --
// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~

module  mux2to1 ( dout, sel, i0, i1 );
  output dout;
  input  sel;
  input  i0, i1;

  reg dout;
 
  always @ (sel or i0 or i1)
  begin
    if (sel) dout <= i1;
    else     dout <= i0;
  end

endmodule

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