// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~// ~ --// ~ Published by: www.asic-digital-design.com// ~ --// ~ Description:// ~ -- This is Verilog description of// ~ -- a multiplexer 4 to 1.// ~ --// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~module mux4to1 ( dout, sel, i0, i1, i2, i3 ); output dout; input [1:0] sel; input i0, i1, i2, i3; reg dout; always @ (sel or i0 or i1 or i2 or i3) begin case (sel) 2'b01: dout <= i1; 2'b10: dout <= i2; 2'b11: dout <= i3; default: dout <= i0; endcase endendmodule |
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