// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
// ~ --
// ~ Published by: www.asic-digital-design.com
// ~ --
// ~ Description:
// ~ -- This is Verilog description of
// ~ -- a multiplexer 8 to 1.
// ~ --
// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
module mux8to1 ( dout, sel, i0, i1, i2, i3,
i4, i5, i6, i7 );
output dout;
input [2:0] sel;
input i0, i1, i2, i3, i4, i5, i6, i7;
reg dout;
always @ (sel or i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7)
begin
case (sel)
3'b001: dout <= i1;
3'b010: dout <= i2;
3'b011: dout <= i3;
3'b100: dout <= i4;
3'b101: dout <= i5;
3'b110: dout <= i6;
3'b111: dout <= i7;
default: dout <= i0;
endcase
end
endmodule
| 