// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~// ~ --// ~ Published by: www.asic-digital-design.com// ~ --// ~ Description: This is Verilog description of a D flip-flop.// ~ with asynchronous set/reset// ~ --// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~module ff_d ( dout, din, clk, arst, aset ); output dout; input din; input clk, arst, aset; // declaration of signals inside this block reg reg_ffd; always @ (posedge arst or posedge aset or posedge clk ) // ff_d begin if (arst == 1'b1) reg_ffd <= 1'b0; else if (aset == 1'b1) reg_ffd <= 1'b1; else reg_ffd <= din; end // end ff_d // outputs -- assign dout=reg_ffd; //--endmodule |
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