// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~// ~ --// ~ Published by: www.asic-digital-design.com// ~ --// ~ Description: This is Verilog description of a D latch.// ~ with asynchronous set/reset// ~ --// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~module latch_d ( dout, din, en, arst, aset ); output dout; input din; input en, arst, aset; // declaration of signals inside this block reg reg_latch; always @ (arst or aset or en or din) // latch_d begin if (arst) reg_latch <= 1'b0; else if (aset) reg_latch <= 1'b1; else if (en) reg_latch <= din; end // end latch_d // outputs -- assign dout=reg_latch; //--endmodule |
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