// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
// ~ --
// ~ Published by:   www.asic-digital-design.com
// ~ --
// ~ Description: This is synchronous n-bit binary counter
// ~              with possibility to count UP or DOWN.
// ~                UP: dir='1'
// ~                DOWN: dir='0'
// ~ --
// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~

module  cnt_bindir ( dout, dir, clk, arst, srst, en );
  parameter  [31:0]  n = 8;
  output [(n - 1):0] dout;
  input  dir;
  input  clk, arst, srst, en;

  // declaration of signals inside this block
  reg  [(n - 1):0] reg_cnt;
  reg  [(n - 1):0] nxt_cnt;

  always @ (posedge arst or posedge clk ) // dff_cnt
  begin
    if ((arst == 1'b1)) reg_cnt <= {((n - 1)-0+1- 0){1'b0}};
    else
      if ((srst == 1'b1)) reg_cnt <= {((n - 1)-0+1- 0){1'b0}};
      else
        if ((en == 1'b1)) reg_cnt <= nxt_cnt;
  end
  // end dff_cnt 

  always @ (reg_cnt or dir ) // cmb_cnt
  begin
    if ((dir == 1'b0)) 
      nxt_cnt <= (reg_cnt + 1);
    else 
      nxt_cnt <= (reg_cnt - 1);
  end
  // end cmb_cnt 

  // outputs --
  assign {dout}=reg_cnt;
  //--
endmodule