// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~// ~ --// ~ Published by: www.asic-digital-design.com// ~ --// ~ Description: This is synchronous Johnson counter.// ~ --// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~module cnt_john ( dout, clk, arst, srst, en ); parameter [31:0] n = 8; output [(n - 1):0] dout; input clk, arst, srst, en; // declaration of signals inside this block reg [(n - 1):0] reg_john; reg [(n - 1):0] nxt_john; always @ (posedge arst or posedge clk ) // dff_john begin if ((arst == 1'b1)) reg_john <= {((n - 1)-0+1- 0){1'b0}}; else if ((srst == 1'b1)) reg_john <= {((n - 1)-0+1- 0){1'b0}}; else if ((en == 1'b1)) reg_john <= nxt_john; end // end dff_john always @ (reg_john) // cmb_john begin nxt_john <= {reg_john[(n - 2):0],~ (reg_john[(n - 1)])}; end // end cmb_john // outputs -- assign {dout}=reg_john; //--endmodule |
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