// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~// ~ --// ~ Published by: www.asic-digital-design.com// ~ --// ~ Description: This is reset generator model.// ~ --// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~module reset_gen ( arst ); output arst; parameter param_reset_delay = 25; reg arst_i; // reset generation initial begin {arst_i}<=1'b1; #(param_reset_delay) {arst_i}<=1'b0; end //end initial // outputs -- assign {arst}=arst_i; //--endmodule |
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Verilog: reset generator |