Bitwise ~ 1's complement & Bitwise AND | Bitwise OR ^ Bitwise XOR ~^ or ^~ Bitwise XNORLogical ! NOT && AND || ORReduction & Reduction AND ~& Reduction NAND | Reduction OR ~| Reduction NOR ^ Reduction XOR ~^ or ^~ Reduction XNORArithmetic + Addition - Subtraction - 2's complement * Multiplication / Division ** exponent (*Verilog-2001)Relational > Greater than < Less than >= Greater than or equal to <= Less than or equal to == logical equality (bit-value 1'bX is removed from comparison) != Logical inequality (bit-value 1'bX is removed from comparison) === 4-state logical equality (bit-value 1'bX is taken as literal) !== 4-state Logical inequality (bit-value 1'bX is taken as literal)Shift >> Logical Right shift << Logical Left shift >>> Arithmetic Right shift (*Verilog-2001) <<< Arithmetic Left shift (*Verilog-2001)
Concatenation { , } ConcatenationReplication {{ }} ReplicationConditional ? : Conditional |
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