-- ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
-- ~ --
-- ~ Published by:   www.asic-digital-design.com
-- ~ --
-- ~ Description: This is synchronous shift register.
-- ~ --
-- ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- ~ --
entity shift_register is
  generic ( n : natural := 8 );
  port (
    dout                 : out std_logic_vector(n-1 downto 0);
    din                  : in  std_logic;
    clk, arst, srst, en  : in  std_logic );
end;
-- ~ --
architecture rtl of shift_register is
  -- declaration of signals inside this block
  signal reg_shifter, nxt_shifter : std_logic_vector(n-1 downto 0);
begin

  dff_shifter: process(arst, clk)
  begin
    if (arst = '1') then
      reg_shifter    <= (others => '0');
    elsif (clk'event and clk = '1') then
      if (srst = '1') then
        reg_shifter    <= (others => '0');
      else
        if (en = '1') then
          reg_shifter <= nxt_shifter;
        end if;
      end if;
    end if;
  end process;

  cmb_shifter: process(reg_shifter, din)
  begin
    nxt_shifter <= reg_shifter(n-2 downto 0) & din;
  end process;

  -- outputs --
  dout <= reg_shifter;
  -- ~ --
end rtl;