-- ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
-- ~ --
-- ~ Published by:   www.asic-digital-design.com
-- ~ --
-- ~ Description: This is synchronous n-bit 1 of N counter.
-- ~ --
-- ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- ~ --
entity shift_1ofn is
  generic ( n : natural := 8 );
  port (
    dout                 : out std_logic_vector(n-1 downto 0);
    clk, arst, srst, en  : in  std_logic );
end;
-- ~ --
architecture rtl of shift_1ofn is
  -- declaration of signals inside this block
  signal reg_1ofn, nxt_1ofn : std_logic_vector(n-1 downto 0);
begin

  dff_1ofn: process(arst, clk)
  begin
    if (arst = '1') then
      reg_1ofn    <= (others => '0');
      reg_1ofn(0) <= '1';
    elsif (clk'event and clk = '1') then
      if (srst = '1') then
        reg_1ofn    <= (others => '0');
        reg_1ofn(0) <= '1';
      else
        if (en = '1') then
          reg_1ofn <= nxt_1ofn;
        end if;
      end if;
    end if;
  end process;

  cmb_1ofn: process(reg_1ofn)
  begin
    if (reg_1ofn(n-1) = '1') then
      nxt_1ofn <= reg_1ofn(n-2 downto 0) & '1';
    else
      nxt_1ofn <= reg_1ofn(n-2 downto 0) & '0';
    end if;
  end process;

  -- outputs --
  dout <= reg_1ofn;
  -- ~ --
end rtl;