-- ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
-- ~ --
-- ~ Published by:   www.asic-digital-design.com
-- ~ --
-- ~ Description: This is synchronous n-bit binary counter
-- ~              with possibility to count UP or DOWN.
-- ~                UP: dir='1'
-- ~                DOWN: dir='0'
-- ~ --
-- ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- ~ --
entity cnt_bindir is
  generic ( n : natural := 8 );
  port (
    dout                 : out std_logic_vector(n-1 downto 0);
    dir                  : in  std_logic;
    clk, arst, srst, en  : in  std_logic );
end;
-- ~ --
architecture rtl of cnt_bindir is
  -- declaration of signals inside this block
  signal reg_cnt, nxt_cnt : std_logic_vector(n-1 downto 0);
begin
--
  dff_cnt: process(arst, clk)
  begin
    if (arst = '1') then reg_cnt <= (others => '0');
    elsif (clk'event and clk = '1') then
      if (srst = '1') then reg_cnt <= (others => '0');
      else
        if (en = '1') then
          reg_cnt <= nxt_cnt;
        end if;
      end if;
    end if;
  end process;

  cmb_cnt: process(reg_cnt, dir)
  begin
    if (dir = '0') then
      nxt_cnt <= reg_cnt + 1;
    else
      nxt_cnt <= reg_cnt - 1;
    end if;
  end process;

  -- outputs --
  dout <= reg_cnt;
  -- ~ --
end rtl;